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| author | LiDongjin <jin.mse.sse@gmail.com> | 2023-01-06 09:54:19 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-01-06 09:54:19 -0800 |
| commit | 4554663bc0da71d61ab488641c95ef98430cb451 (patch) | |
| tree | cfda091b9e79fca307e6e1dfc78d75ba8f65221d /llvm/lib/CodeGen/MachineOperand.cpp | |
| parent | 968f2c77a8cd562744e93948a5a854244ccd96e5 (diff) | |
| download | llvm-4554663bc0da71d61ab488641c95ef98430cb451.zip llvm-4554663bc0da71d61ab488641c95ef98430cb451.tar.gz llvm-4554663bc0da71d61ab488641c95ef98430cb451.tar.bz2 | |
Recommit "[RISCV] Enable the LocalStackSlotAllocation pass support"
This includes a fix for the tramp3d failure from the llvm-testsuite
that caused the last revert. Hopefully the others failures were the
same issue.
Original commit message:
For RISC-V, load/store(exclude vector load/store) instructions only has a 12 bit immediate operand. If the offset is out-of-range, it must make use of a temp register to make up this offset. If between these offsets, they have a small(IsInt<12>) relative offset, LocalStackSlotAllocation pass can find a value as frame base register's value, and replace the origin offset with this register's value plus the relative offset.
Co-authored-by: luxufan <luxufan@iscas.ac.cn>
Co-authored-by: Craig Topper <craig.topper@sifive.com>
Differential Revision: https://reviews.llvm.org/D98101
Diffstat (limited to 'llvm/lib/CodeGen/MachineOperand.cpp')
0 files changed, 0 insertions, 0 deletions