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| author | Craig Topper <craig.topper@sifive.com> | 2023-01-06 08:29:23 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-01-06 08:29:23 -0800 |
| commit | 1aa9862df3634d1d526e5bfd0431408a24ac435a (patch) | |
| tree | bcd09d7ab156555e4fbb1ee2c9c7fe07f7a4ef57 /llvm/lib/CodeGen/MachineOperand.cpp | |
| parent | d18a2dc5c9757aa32a202c1f98a8dea21ac8ca80 (diff) | |
| download | llvm-1aa9862df3634d1d526e5bfd0431408a24ac435a.zip llvm-1aa9862df3634d1d526e5bfd0431408a24ac435a.tar.gz llvm-1aa9862df3634d1d526e5bfd0431408a24ac435a.tar.bz2 | |
[RISCV] Add more XVentanaCondOps patterns.
Add patterns with seteq/setne conditions.
We don't have instructions for seteq/setne except for comparing
with zero and need to emit an ADDI or XOR before a seqz/snez to
compare other values.
The select ISD node takes a 0/1 value for the condition, but the
VT_MASKC(N) instructions check all XLen bits for zero or non-zero.
We can use this to avoid the seqz/snez in many cases.
This is pretty ridiculous number of patterns. I wonder if we could
use some ComplexPatterns to merge them, but I'd like to do that as
a follow up and focus on correctness of the result in this patch.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D140421
Diffstat (limited to 'llvm/lib/CodeGen/MachineOperand.cpp')
0 files changed, 0 insertions, 0 deletions