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| author | Craig Topper <craig.topper@sifive.com> | 2024-10-29 17:46:52 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-29 17:46:52 -0700 |
| commit | 13a3c4f97cf33279d597148ec48c71337aa16e9a (patch) | |
| tree | 7ce9048e9ee6df239bbedabe0756836b820c5d40 /llvm/lib/CodeGen/MachineModuleSlotTracker.cpp | |
| parent | 255e441613e39a391e9f85d6a605cc9e46dcf273 (diff) | |
| download | llvm-13a3c4f97cf33279d597148ec48c71337aa16e9a.zip llvm-13a3c4f97cf33279d597148ec48c71337aa16e9a.tar.gz llvm-13a3c4f97cf33279d597148ec48c71337aa16e9a.tar.bz2 | |
[RISCV] Add OperandType to frmarg and rtzarg. (#114142)
Teach RISCVInstrInfo::verifyInstruction to validate them.
This is partially extracted from #89047, but that did not include the
verification.
Diffstat (limited to 'llvm/lib/CodeGen/MachineModuleSlotTracker.cpp')
0 files changed, 0 insertions, 0 deletions