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| author | Luke Lau <luke@igalia.com> | 2024-12-16 11:55:48 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-12-16 11:55:48 +0800 |
| commit | 4746395bd75bc234dfd026bad672613b99e87e7a (patch) | |
| tree | b40981cfec50c32d08032de757cfaf331cf11d29 /llvm/lib/CodeGen/MachineModuleInfoImpls.cpp | |
| parent | f8ad6e0cdae3cbc1618b19c3c7b41021070c0e94 (diff) | |
| download | llvm-4746395bd75bc234dfd026bad672613b99e87e7a.zip llvm-4746395bd75bc234dfd026bad672613b99e87e7a.tar.gz llvm-4746395bd75bc234dfd026bad672613b99e87e7a.tar.bz2 | |
[VPlan] Omit zero add in VPWidenIntOrFpInductionRecipe (#119668)
I'm not sure if getStepVector was used for other things in the past
where StartIdx was non-zero, but nowadays VPWidenIntOrFpInductionRecipe
is the only user of it, and just passes zero to it. I presume
InstCombine was already catching this so hopefully removing this won't
affect codegen.
Diffstat (limited to 'llvm/lib/CodeGen/MachineModuleInfoImpls.cpp')
0 files changed, 0 insertions, 0 deletions