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| author | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2023-04-26 15:18:51 +0200 |
|---|---|---|
| committer | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2023-04-27 09:39:44 +0200 |
| commit | 1e63f8272e8ad2b41f9c4d58250d7de264c4aa4b (patch) | |
| tree | e37f4e564c3d67e3085c61ea05915a455abba91c /llvm/lib/CodeGen/MachineModuleInfoImpls.cpp | |
| parent | da4fcb0c0b281746067f92d8804c18dbce4269bd (diff) | |
| download | llvm-1e63f8272e8ad2b41f9c4d58250d7de264c4aa4b.zip llvm-1e63f8272e8ad2b41f9c4d58250d7de264c4aa4b.tar.gz llvm-1e63f8272e8ad2b41f9c4d58250d7de264c4aa4b.tar.bz2 | |
AMDGPU: Fix an assertion in SIOptimizeVGPRLiveRange
As the comment notes, the shader results in an INSERT_SUBREG with
"undef" (dead) operand in the Endif block. The same can happen with
REG_SEQUENCE. The register is considered dead from a liveness
analysis perspective. The correct thing to do seems to be nothing:
we keep the undef use of the register, the register allocator should
still be able to take the liveness into account correctly.
Differential Revision: https://reviews.llvm.org/D149161
Diffstat (limited to 'llvm/lib/CodeGen/MachineModuleInfoImpls.cpp')
0 files changed, 0 insertions, 0 deletions