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| author | Haocong.Lu <Haocong.Lu@streamcomputing.com> | 2022-03-16 02:07:21 +0000 |
|---|---|---|
| committer | Ben Shi <ben.shi@streamcomputing.com> | 2022-03-16 02:10:57 +0000 |
| commit | 6a54776fe0092c251ee3783c0c25d14699467896 (patch) | |
| tree | 1d3f79eb650f9f60f753c7d415ba83b69b6c7ef3 /llvm/lib/CodeGen/MachineModuleInfo.cpp | |
| parent | e4cab4e24d17e4a434d0edd6d7d037f0d05ced36 (diff) | |
| download | llvm-6a54776fe0092c251ee3783c0c25d14699467896.zip llvm-6a54776fe0092c251ee3783c0c25d14699467896.tar.gz llvm-6a54776fe0092c251ee3783c0c25d14699467896.tar.bz2 | |
[RISCV] Select SRLI+SLLI for AND with leading ones mask
Select SRLI+SLLI for and i64 %x, imm if the imm is a leading ones mask.
It's useful in RV64 when the mask exceeds simm32 (cannot be generated by LUI).
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D121598
Diffstat (limited to 'llvm/lib/CodeGen/MachineModuleInfo.cpp')
0 files changed, 0 insertions, 0 deletions