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| author | Craig Topper <craig.topper@sifive.com> | 2022-03-09 16:43:17 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-03-09 16:43:22 -0800 |
| commit | edd6632127975c61181dc8003c1271d4d86255b1 (patch) | |
| tree | 64107499fc803b832569cf48e4f1472d67196be6 /llvm/lib/CodeGen/MachineFunction.cpp | |
| parent | 0f770f4d00e34249595a68df1be11df87b5149d7 (diff) | |
| download | llvm-edd6632127975c61181dc8003c1271d4d86255b1.zip llvm-edd6632127975c61181dc8003c1271d4d86255b1.tar.gz llvm-edd6632127975c61181dc8003c1271d4d86255b1.tar.bz2 | |
[RISCV] Support 'generic' as a valid CPU name.
Most other targets support 'generic', but RISCV issues an error.
This can require a special case in tools that use LLVM that aren't
clang.
This patch treats "generic" the same as an empty string and remaps
it to generic-rv/rv64 based on the triple. Unfortunately, it has to
be added to RISCV.td because MCSubtargetInfo is constructed and
parses the CPU before RISCVSubtarget's constructor gets a chance
to remap it. The CPU will then reparsed and the state in the
MCSubtargetInfo subclass will be updated again.
Fixes PR54146.
Reviewed By: khchen
Differential Revision: https://reviews.llvm.org/D121149
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions