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| author | Shilei Tian <i@tianshilei.me> | 2024-11-08 20:21:16 -0500 |
|---|---|---|
| committer | Shilei Tian <i@tianshilei.me> | 2024-11-08 20:21:16 -0500 |
| commit | 6548b6354d1d990e1c98736f5e7c3de876bedc8e (patch) | |
| tree | 2e33ea491043626378d48e0149bf0592cbbe327d /llvm/lib/CodeGen/MachineCSE.cpp | |
| parent | b70eb8631386bbccca5a07bb0253aa738d4cda81 (diff) | |
| download | llvm-6548b6354d1d990e1c98736f5e7c3de876bedc8e.zip llvm-6548b6354d1d990e1c98736f5e7c3de876bedc8e.tar.gz llvm-6548b6354d1d990e1c98736f5e7c3de876bedc8e.tar.bz2 | |
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
This reverts commit ca33649abe5fad93c57afef54e43ed9b3249cd86.
Diffstat (limited to 'llvm/lib/CodeGen/MachineCSE.cpp')
0 files changed, 0 insertions, 0 deletions