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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2024-11-08 19:01:59 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-08 19:01:59 -0800 |
| commit | 1bf385f10291101163a346c8f075d56e1578351b (patch) | |
| tree | d5a1afc92f4a4e4cf26aa3415b27fd44b25410d5 /llvm/lib/CodeGen/MachineCSE.cpp | |
| parent | c61832444d7539eddb939df1107a751a6784aff3 (diff) | |
| download | llvm-1bf385f10291101163a346c8f075d56e1578351b.zip llvm-1bf385f10291101163a346c8f075d56e1578351b.tar.gz llvm-1bf385f10291101163a346c8f075d56e1578351b.tar.bz2 | |
AMDGPU: Default to selecting frame indexes to SGPRs (#115060)
Only select to a VGPR if it's trivally used in VGPR only contexts.
This fixes mishandling frame indexes used in SGPR only contexts,
like inline assembly constraints.
This is suboptimal in the common case where the frame index
is transitively used by only VALU ops. We make up for this by later
folding the copy to VALU plus scalar op in SIFoldOperands.
Diffstat (limited to 'llvm/lib/CodeGen/MachineCSE.cpp')
0 files changed, 0 insertions, 0 deletions