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| author | hev <wangrui@loongson.cn> | 2025-05-22 18:49:27 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-05-22 18:49:27 +0800 |
| commit | bd8578c3574d77bc1231f047bced4a0053a1b000 (patch) | |
| tree | d0065179ebb267b635b3f74d6fa2cf8c0463bfed /llvm/lib/CodeGen/MachineBasicBlock.cpp | |
| parent | 7a3b5d789d5fee6fe9883b6a3cb9d2ede4262276 (diff) | |
| download | llvm-bd8578c3574d77bc1231f047bced4a0053a1b000.zip llvm-bd8578c3574d77bc1231f047bced4a0053a1b000.tar.gz llvm-bd8578c3574d77bc1231f047bced4a0053a1b000.tar.bz2 | |
[LoongArch] Prevent R0/R1 allocation for rj operand of [G]CSRXCHG (#140862)
The `[G]CSRXCHG` instruction must not use R0 or R1 as the `rj` operand,
as encoding `rj` as 0 or 1 will be interpreted as `[G]CSRRD` OR
`[G]CSRWR`, respectively, rather than `[G]CSRXCHG`.
This patch introduces a new register class `GPRNoR0R1` and updates the
`[G]CSRXCHG` instruction definition to use it for the `rj` operand,
ensuring the register allocator avoids assigning R0 or R1.
Fixes #140842
Diffstat (limited to 'llvm/lib/CodeGen/MachineBasicBlock.cpp')
0 files changed, 0 insertions, 0 deletions