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| author | Sameer Sahasrabuddhe <sameer.sahasrabuddhe@amd.com> | 2023-07-27 14:49:17 +0530 |
|---|---|---|
| committer | Sameer Sahasrabuddhe <sameer.sahasrabuddhe@amd.com> | 2023-07-27 14:49:17 +0530 |
| commit | 7c760b224bc4581a7a962ae7ded098a260d19500 (patch) | |
| tree | c34f443341bc1f10ff006954a7d8b002b67d3234 /llvm/lib/CodeGen/MachineBasicBlock.cpp | |
| parent | 4cd7d8e30aca25c86ff40cd547f78b27d573a503 (diff) | |
| download | llvm-7c760b224bc4581a7a962ae7ded098a260d19500.zip llvm-7c760b224bc4581a7a962ae7ded098a260d19500.tar.gz llvm-7c760b224bc4581a7a962ae7ded098a260d19500.tar.bz2 | |
Restore "[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR"
Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic
ID is the first non-def operand to the instruction. These are now represented as
a subclass of GenericMachineInstr, and the method MachineInstr::getIntrinsicID()
is now moved to this subclass GIntrinsic.
Some target-defined instructions behave like GMIR intrinsics, and have an
Intrinsic::ID operand. But they should not be recognized as generic intrinsics,
and should not use GIntrinsic::getIntrinsicID(). Separated these out by
introducing a new AMDGPU::getIntrinsicID().
Reviewed By: arsenm, Pierre-vh
Differential Revision: https://reviews.llvm.org/D155556
This restores commit baa3386edb11a2f9bcadda8cf58d56f3707c39fa.
Originally reverted in d0f7850b01cf17e50a4f4b00e3b84dded94df6b8.
Diffstat (limited to 'llvm/lib/CodeGen/MachineBasicBlock.cpp')
0 files changed, 0 insertions, 0 deletions