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authorJeremy Morse <jeremy.morse@sony.com>2022-04-26 11:08:05 +0100
committerJeremy Morse <jeremy.morse@sony.com>2022-04-26 15:49:22 +0100
commit65d5beca13e65b4ae5f421b6d6b8e38bee210544 (patch)
treec271e5c370925f368f88d45e59ede8e7e6313e3c /llvm/lib/CodeGen/LiveDebugVariables.cpp
parent39ce68886b4900dc63a90e90561ee19f5c7c07dc (diff)
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Reapply D124184, [DebugInfo][InstrRef] Add a size operand to DBG_PHI
This was reverted twice, in 987cd7c3ed75b and 13815e8cbf8d4. The latter stemed from not accounting for rare register classes in a pre-allocated array, and the former from an array not being completely initialized, leading to asan complaining.
Diffstat (limited to 'llvm/lib/CodeGen/LiveDebugVariables.cpp')
-rw-r--r--llvm/lib/CodeGen/LiveDebugVariables.cpp21
1 files changed, 19 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/LiveDebugVariables.cpp b/llvm/lib/CodeGen/LiveDebugVariables.cpp
index ce350b7..320e682 100644
--- a/llvm/lib/CodeGen/LiveDebugVariables.cpp
+++ b/llvm/lib/CodeGen/LiveDebugVariables.cpp
@@ -1850,16 +1850,33 @@ void LDVImpl::emitDebugValues(VirtRegMap *VRM) {
const TargetRegisterClass *TRC = MRI.getRegClass(Reg);
unsigned SpillSize, SpillOffset;
- // Test whether this location is legal with the given subreg.
+ unsigned regSizeInBits = TRI->getRegSizeInBits(*TRC);
+ if (SubReg)
+ regSizeInBits = TRI->getSubRegIdxSize(SubReg);
+
+ // Test whether this location is legal with the given subreg. If the
+ // subregister has a nonzero offset, drop this location, it's too complex
+ // to describe. (TODO: future work).
bool Success =
TII->getStackSlotRange(TRC, SubReg, SpillSize, SpillOffset, *MF);
- if (Success) {
+ if (Success && SpillOffset == 0) {
auto Builder = BuildMI(*OrigMBB, OrigMBB->begin(), DebugLoc(),
TII->get(TargetOpcode::DBG_PHI));
Builder.addFrameIndex(VRM->getStackSlot(Reg));
Builder.addImm(InstNum);
+ // Record how large the original value is. The stack slot might be
+ // merged and altered during optimisation, but we will want to know how
+ // large the value is, at this DBG_PHI.
+ Builder.addImm(regSizeInBits);
+ }
+
+ LLVM_DEBUG(
+ if (SpillOffset != 0) {
+ dbgs() << "DBG_PHI for Vreg " << Reg << " subreg " << SubReg <<
+ " has nonzero offset\n";
}
+ );
}
// If there was no mapping for a value ID, it's optimized out. Create no
// DBG_PHI, and any variables using this value will become optimized out.