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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-10-28 12:26:27 -0700 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2019-10-28 20:51:51 -0700 |
| commit | 21bc8e5a137d76879223ac2d8ff1ba92e2ea3acb (patch) | |
| tree | 8de44986f0f9c5dc77cca2ed66dd816ea76e2be8 /llvm/lib/CodeGen/LiveDebugValues.cpp | |
| parent | c1498e37abe6ff1f3e338551c1d94d294a7e5ac4 (diff) | |
| download | llvm-21bc8e5a137d76879223ac2d8ff1ba92e2ea3acb.zip llvm-21bc8e5a137d76879223ac2d8ff1ba92e2ea3acb.tar.gz llvm-21bc8e5a137d76879223ac2d8ff1ba92e2ea3acb.tar.bz2 | |
AMDGPU: Make VReg_1 only include 1 artificial register
When TableGen is inferring register classes from contexts, it uses a
sorting function based on the number of registers in the class. Since
this was being treated as an alias of VGPR_32, they had exactly the
same size. The sort used wasn't a stable sort, and even if it were, I
believe the tie breaker would effectively end up being the
alphabetical ordering of the class name. There appear to be issues
trying to use an empty set of registers, so add only one so this will
always sort to the end.
Also add a comment explaining how VReg_1 is a dirty hack for
SelectionDAG.
This does end up changing the behavior of i1 with inline asm and VGPR
constraints, but the existing behavior was was already nonsensical and
inconsistent. It should probably be disallowed anyway.
Fixes bug 43699
Diffstat (limited to 'llvm/lib/CodeGen/LiveDebugValues.cpp')
0 files changed, 0 insertions, 0 deletions