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author | Pengcheng Wang <wangpengcheng.pp@bytedance.com> | 2025-03-13 12:27:59 +0800 |
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committer | GitHub <noreply@github.com> | 2025-03-13 12:27:59 +0800 |
commit | 08a3c532255d2af8722c32a7484a8648ac0ae2f5 (patch) | |
tree | fe527eb1a358331a1a59eb9c8e35dc00cd0bb904 /llvm/lib/CodeGen/DFAPacketizer.cpp | |
parent | 3438dfc7ff8863bdd8c34e41d0cade5ca4581891 (diff) | |
download | llvm-08a3c532255d2af8722c32a7484a8648ac0ae2f5.zip llvm-08a3c532255d2af8722c32a7484a8648ac0ae2f5.tar.gz llvm-08a3c532255d2af8722c32a7484a8648ac0ae2f5.tar.bz2 |
[RegAlloc] Scale the spill weight by target factor (#113675)
Currently, the spill weight is only determined by isDef/isUse and
block frequency. However, for registers with different register
classes, the costs of spilling them are different.
For example, for `LMUL>1` registers (in which, several physical
registers compound a bigger logical register), the costs are larger
than `LMUL=1` case (in which, there is only one physical register).
To solve this problem, a new target hook `getSpillWeightScaleFactor`
is added. Targets can override the default factor (which is `1.0`)
according to the register class.
For RISC-V, the factors are set to the `RegClassWeight` which is
used to track register pressure. The values of `RegClassWeight`
happen to be the number of register units.
I believe all of the targets with compounded registers can benefit
from this change, but only RISC-V is customized in this patch since
it has widely been agreed to do so. The other targets need more
performance data to go further.
Partially fixes #113489.
Diffstat (limited to 'llvm/lib/CodeGen/DFAPacketizer.cpp')
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