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| author | Hank Chang <hank.chang@sifive.com> | 2025-03-13 15:07:07 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-13 15:07:07 +0800 |
| commit | bd748b33958f8889d280afd4396b189edd0745bf (patch) | |
| tree | dcf6085c88ff1dfa9447f69dc1227d4e156a8c46 /llvm/lib/CodeGen/CodeGen.cpp | |
| parent | 6345b009c3e58a6cd0eca835d5a935f8784cfda6 (diff) | |
| download | llvm-bd748b33958f8889d280afd4396b189edd0745bf.zip llvm-bd748b33958f8889d280afd4396b189edd0745bf.tar.gz llvm-bd748b33958f8889d280afd4396b189edd0745bf.tar.bz2 | |
[RISCV] Add implicit operand {VL, VTYPE} in RISCVInsertVSETVLI when u… (#130733)
…sing inline assembly.
Fixing [#128636](https://github.com/llvm/llvm-project/pull/128636).
This patch has RISCVInsertVSETVLI to add implicit use operand to inline
assembly, this approach is suggested by @preames and the implementation
I referenced is from @topperc . The purpose of adding vl, vtype implicit
operand is to prevent Post-RA scheduler moving vsetvl across inline
assembly.
Diffstat (limited to 'llvm/lib/CodeGen/CodeGen.cpp')
0 files changed, 0 insertions, 0 deletions