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| author | Lukacma <Marian.Lukac@arm.com> | 2024-10-23 11:34:50 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-23 11:34:50 +0100 |
| commit | 2c5208a2dc4aaa5615e6c19e3f417f4727f4b65b (patch) | |
| tree | 1a941150eaf95475cd25ada2d0183959b5eaa94c /llvm/lib/CodeGen/CodeGen.cpp | |
| parent | a59f7124349fc42e6aa8031796f310bb883d95de (diff) | |
| download | llvm-2c5208a2dc4aaa5615e6c19e3f417f4727f4b65b.zip llvm-2c5208a2dc4aaa5615e6c19e3f417f4727f4b65b.tar.gz llvm-2c5208a2dc4aaa5615e6c19e3f417f4727f4b65b.tar.bz2 | |
[LLVM][AARCH64] Add assembly/disassembly of zeroing convert instructions (#113292)
This patch adds the zeroing predicate forms (Pg/z) of the following
instructions:
- FCVTXNT
- FCVTNT
- FCVTLT
- BFCVTNT
As specified in https://developer.arm.com/documentation/ddi0602.
Co-authored-by: Spencer Abson
[spencer.abson@arm.com](mailto:spencer.abson@arm.com)
Diffstat (limited to 'llvm/lib/CodeGen/CodeGen.cpp')
0 files changed, 0 insertions, 0 deletions