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| author | wanglei <wanglei@loongson.cn> | 2022-12-13 11:32:10 +0800 |
|---|---|---|
| committer | wanglei <wanglei@loongson.cn> | 2022-12-13 11:46:53 +0800 |
| commit | 899226adac2cd07938b318e100fdca1eb9c4b1e1 (patch) | |
| tree | b008138df87117b7ca4d4f0a829d49b95970350b /llvm/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp | |
| parent | 01e4f41b43b57dee751146fde9992c660bd7c714 (diff) | |
| download | llvm-899226adac2cd07938b318e100fdca1eb9c4b1e1.zip llvm-899226adac2cd07938b318e100fdca1eb9c4b1e1.tar.gz llvm-899226adac2cd07938b318e100fdca1eb9c4b1e1.tar.bz2 | |
[LoongArch] Add custom parser for atomic instructions' memory operand
In order to be compatible with the form of the atomic instruction in
GAS that accepts the fourth operand as 0 (i.e. `am* $rd, $rk, $rj, 0`),
we need to treat `$rj, 0` as one operand, but only print `$rj`.
For this, the number of result operands of inline assembly memory
operand `ZB` constraint is modified to 2 (reg + 0).
Restrictions on register usage in `am*` instructions have also been
adjusted. When `$rd` is equal to `$r0`, the instruction must be
considered legal, because of some special usage like `PseudoUNIMP`.
Reviewed By: SixWeining, xen0n
Differential Revision: https://reviews.llvm.org/D139303
Diffstat (limited to 'llvm/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp')
0 files changed, 0 insertions, 0 deletions