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| author | Luke Lau <luke@igalia.com> | 2025-09-05 08:25:48 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-05 00:25:48 +0000 |
| commit | dc2ed0043295a397d680db091c2033a51d21e32e (patch) | |
| tree | 0403d11d1c9e2d3ff2b8c22175605b09b9978027 /llvm/lib/CodeGen/AsmPrinter | |
| parent | 4e5e65e55dc5a5ffc6e3db321df7f118e1c42d38 (diff) | |
| download | llvm-main.zip llvm-main.tar.gz llvm-main.tar.bz2 | |
If a VL operand is > 31 then it will be materialized into an ADDI $x0,
imm. We can reason about it by peeking at the virtual register
definition which allows RISCVVectorPeephole and RISCVVLOptimizer to
catch more cases.
There's a separate issue with RISCVVLOptimizer where the materialized
immediate may not always dominate the instruction we want to reduce the
VL of, but this is left to another patch.
Diffstat (limited to 'llvm/lib/CodeGen/AsmPrinter')
0 files changed, 0 insertions, 0 deletions