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| author | Luke Lau <luke@igalia.com> | 2025-07-22 15:21:42 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-22 15:21:42 +0800 |
| commit | eafe31b293a5166522fff4f3e2d88c2b5c881381 (patch) | |
| tree | de946d7e08206bf2786e2eb88d3103e893e3fc24 /llvm/lib/Bitcode | |
| parent | 95201b2b6445e49cf9b470fe93d62e9b3f6efed5 (diff) | |
| download | llvm-eafe31b293a5166522fff4f3e2d88c2b5c881381.zip llvm-eafe31b293a5166522fff4f3e2d88c2b5c881381.tar.gz llvm-eafe31b293a5166522fff4f3e2d88c2b5c881381.tar.bz2 | |
[RISCV] Don't lose elements from False in vmerge -> vmv peephole (#149720)
In the vmerge peephole, we currently allow different AVLs for the vmerge
and its true operand.
If vmerge's VL > true's VL, vmerge can "preserve" elements from false
that would otherwise be clobbered with a tail agnostic policy on true.
mask 1 1 1 1 0 0 0 0
true x x x x|. . . . AVL=4
vmerge x x x x f f|. . AVL=6
If we convert this to vmv.v.v we will lose those false elements:
mask 1 1 1 1 0 0 0 0
true x x x x|. . . . AVL=4
vmv.v.v x x x x . .|. . AVL=6
Fix this by checking that vmerge's AVL is <= true's AVL.
Should fix #149335
Diffstat (limited to 'llvm/lib/Bitcode')
0 files changed, 0 insertions, 0 deletions