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| author | Mel Chen <mel.chen@sifive.com> | 2025-07-22 14:56:14 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-22 14:56:14 +0800 |
| commit | d2a7f4e528c9a8a2ac480c13259bd6050f59d4a7 (patch) | |
| tree | 0098af00ac84fcf1a6a2c44e4ed3edbe8fcce85a /llvm/lib/Bitcode | |
| parent | d87bf79a236f25bccebca9ceaff7fb51399df052 (diff) | |
| download | llvm-d2a7f4e528c9a8a2ac480c13259bd6050f59d4a7.zip llvm-d2a7f4e528c9a8a2ac480c13259bd6050f59d4a7.tar.gz llvm-d2a7f4e528c9a8a2ac480c13259bd6050f59d4a7.tar.bz2 | |
[NFC][LV] Refine the lit test case riscv-vector-reverse.ll (#149020)
This patch includes the following changes:
1. Merge riscv-vector-reverse-output.ll into riscv-vector-reverse.ll,
and only check the generated LLVM IR.
2. Add vplan-riscv-vector-reverse.ll to preserve the original debug
output checks from riscv-vector-reverse.ll.
Diffstat (limited to 'llvm/lib/Bitcode')
0 files changed, 0 insertions, 0 deletions