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| author | Charitha Saumya <136391709+charithaintc@users.noreply.github.com> | 2025-04-30 12:16:47 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-30 12:16:47 -0700 |
| commit | d30554b19edc27bc9ca3475b888c1b3e4eda87c4 (patch) | |
| tree | 98d8e329d0e12aea284a817b08c4e691bccea732 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 1531dfcb3a953b7b3187bca7e58e4e18def58d7d (diff) | |
| download | llvm-d30554b19edc27bc9ca3475b888c1b3e4eda87c4.zip llvm-d30554b19edc27bc9ca3475b888c1b3e4eda87c4.tar.gz llvm-d30554b19edc27bc9ca3475b888c1b3e4eda87c4.tar.bz2 | |
[mlir][xegpu] SIMT distribution patterns for XeGPU CreateNdTdesc, LoadNd, StoreNd and Dpas Ops. (#135271)
This PR adds the SIMT distribution patterns for create_nd_tdesc, load_nd, store_nd and dpas XeGPU ops.
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions