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author | Youngsuk Kim <youngsuk.kim@hpe.com> | 2024-11-18 17:12:19 -0500 |
---|---|---|
committer | GitHub <noreply@github.com> | 2024-11-18 17:12:19 -0500 |
commit | b083340cb663b6bd785dbd5864e5afd950745e35 (patch) | |
tree | 30c59b76aa92b4f270151447ed627b475c02ff13 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
parent | ad9c0b369e86e75d56e229f294782a4eaf527226 (diff) | |
download | llvm-b083340cb663b6bd785dbd5864e5afd950745e35.zip llvm-b083340cb663b6bd785dbd5864e5afd950745e35.tar.gz llvm-b083340cb663b6bd785dbd5864e5afd950745e35.tar.bz2 |
[llvm][NVPTX] Don't reorder MIs that construct a PTX function call (#116522)
With "-enable-misched", MachineScheduler can reorder MIs that must stick
together (in initially set order) to generate legal PTX code for a
function call.
When generating PTX code for the attached test (using LLVM before this
revision), the following invalid PTX code is generated:
```
{ // callseq 0, 0
.param .b64 param0;
st.param.f64 [param0], 0d0000000000000000;
.param .b64 retval0;
call.uni (retval0),
mul.lo.s32 %r7, %r10, %r3;
or.b32 %r8, %r4, %r7;
mul.lo.s32 %r9, %r2, %r8;
cvt.rn.f64.s32 %fd3, %r9;
quux,
(
param0
);
ld.param.f64 %fd1, [retval0];
} // callseq 0
```
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions