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| author | arthurqiu <arthurq@nvidia.com> | 2024-11-21 01:31:01 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-20 18:31:01 +0100 |
| commit | 81055ff070e128bff78c8fa2d8ffe4c92ae692a6 (patch) | |
| tree | e18635ab16808bee7350b42e53294f9c87241837 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 0733f384142b02558b80b3e9a4633dc4d202a14b (diff) | |
| download | llvm-81055ff070e128bff78c8fa2d8ffe4c92ae692a6.zip llvm-81055ff070e128bff78c8fa2d8ffe4c92ae692a6.tar.gz llvm-81055ff070e128bff78c8fa2d8ffe4c92ae692a6.tar.bz2 | |
[mlir][nvvm] Add attributes for cluster dimension PTX directives (#116973)
PTX programming models provides cluster dimension directives, which are
leveraged by the downstream `ptxas` compiler. See
https://docs.nvidia.com/cuda/nvvm-ir-spec/#supported-properties and
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#cluster-dimension-directives
This PR introduces the cluster dimension directives to MLIR's NVVM
dialect as listed below:
```
cluster_dim_{x,y,z} -> exact number of CTAs per cluster
cluster_max_blocks -> max number of CTAs per cluster
```
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions