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| author | Srinivasa Ravi <srinivasar@nvidia.com> | 2025-03-12 08:50:12 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-12 08:50:12 +0530 |
| commit | 725726171240afa76166392d105900040a00c5b4 (patch) | |
| tree | 4be07373f89773965d5ca4c3e97ba4babe48267c /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | adae90ee35ca6f60e99189dea95cb719b4969860 (diff) | |
| download | llvm-725726171240afa76166392d105900040a00c5b4.zip llvm-725726171240afa76166392d105900040a00c5b4.tar.gz llvm-725726171240afa76166392d105900040a00c5b4.tar.bz2 | |
[NVPTX] Fix generic address in st.bulk intrinsic (#130740)
This PR fixes an oversight from the previous change (PR #128856) that
introduced the `st.bulk` intrinsic where `llvm_global_ptr_ty` was used
instead of `llvm_ptr_ty` for generic addressing.
PTX Spec Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-st-bulk
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions