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| author | Jonathan Thackray <jonathan.thackray@arm.com> | 2025-04-30 22:06:37 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-30 22:06:37 +0100 |
| commit | 6e49f73825f1b9cb98352a7c8dca3e0cf83ebd9e (patch) | |
| tree | 854e2a21de5728cc71797b49dadf83ddcacb8212 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 9b0eaf71e674a28ee55be3afa11b5f7d4da732c0 (diff) | |
| download | llvm-6e49f73825f1b9cb98352a7c8dca3e0cf83ebd9e.zip llvm-6e49f73825f1b9cb98352a7c8dca3e0cf83ebd9e.tar.gz llvm-6e49f73825f1b9cb98352a7c8dca3e0cf83ebd9e.tar.bz2 | |
Reland [llvm] Add support for llvm IR atomicrmw fminimum/fmaximum instructions (#137701)
This patch adds support for LLVM IR atomicrmw `fmaximum` and `fminimum`
instructions.
These mirror the `llvm.maximum.*` and `llvm.minimum.*` instructions, but
are atomic and use IEEE754 2019 handling for NaNs, which is different to
`fmax` and `fmin`. See:
https://llvm.org/docs/LangRef.html#llvm-minimum-intrinsic
for more details.
Future changes will allow this LLVM IR to be lowered to specialised
assembler instructions on suitable targets, such as AArch64.
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
| -rw-r--r-- | llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp index 5226db9..27ada0d 100644 --- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp +++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp @@ -678,6 +678,10 @@ static unsigned getEncodedRMWOperation(AtomicRMWInst::BinOp Op) { case AtomicRMWInst::FSub: return bitc::RMW_FSUB; case AtomicRMWInst::FMax: return bitc::RMW_FMAX; case AtomicRMWInst::FMin: return bitc::RMW_FMIN; + case AtomicRMWInst::FMaximum: + return bitc::RMW_FMAXIMUM; + case AtomicRMWInst::FMinimum: + return bitc::RMW_FMINIMUM; case AtomicRMWInst::UIncWrap: return bitc::RMW_UINC_WRAP; case AtomicRMWInst::UDecWrap: |