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authorDaniel Zabawa <daniel.zabawa@intel.com>2025-03-21 12:50:12 -0400
committerGitHub <noreply@github.com>2025-03-22 00:50:12 +0800
commit5afa0fa9a6ba482cdc87945b71f5cd626b754d8f (patch)
treebf41a227f061c26f68571c5b2c90dcab7cf03768 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
parentb858ba0f6597c66e5c276ca9e2564ca27e7e28e7 (diff)
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[X86] Prevent APX NDD compression when it creates a partial write (#132051)
APX NDD instructions may be compressed when the result is also a source. For 8/16b instructions, this may create partial register write hazards if a previous super-register def is within the partial reg update clearance, or incorrect code if the super-register is not dead. This change prevents compression when the super-register is marked as an implicit define, which the virtual rewriter already adds in the case where a subregister is defined but the super-register is not dead. The BreakFalseDeps interface is also updated to add implicit super-register defs for NDD instructions that would incur partial-write stalls if compressed to legacy ops.
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
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