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| author | Alex MacLean <amaclean@nvidia.com> | 2024-11-18 13:47:08 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-18 13:47:08 -0800 |
| commit | 55876278d362020503db5f0e66313829c40ff640 (patch) | |
| tree | ab9460f49a4e6838e1b246e8df9ba0fef5477d98 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 31aa7f34e07c901773993dac0f33568307f96da6 (diff) | |
| download | llvm-55876278d362020503db5f0e66313829c40ff640.zip llvm-55876278d362020503db5f0e66313829c40ff640.tar.gz llvm-55876278d362020503db5f0e66313829c40ff640.tar.bz2 | |
[NVPTX] Add support for f16 fabs (#116107)
Add support for f16 and f16x2 support for abs. See PTX ISA 9.7.4.6. Half
Precision Floating Point Instructions: abs
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#half-precision-floating-point-instructions-abs
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions