diff options
| author | Fabian Ritter <fabian.ritter@amd.com> | 2025-01-20 15:47:11 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-01-20 15:47:11 +0100 |
| commit | cc5eba1737146a727a61b5dbe16d8c2ac453981e (patch) | |
| tree | e6089104c6c28184f2009a3d5d78cce280b61b15 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | fcec8756e25333b6f49472f00e043f2389736c0b (diff) | |
| download | llvm-cc5eba1737146a727a61b5dbe16d8c2ac453981e.zip llvm-cc5eba1737146a727a61b5dbe16d8c2ac453981e.tar.gz llvm-cc5eba1737146a727a61b5dbe16d8c2ac453981e.tar.bz2 | |
[AMDGPU] Reject misaligned SGPR constraints for inline asm (#123590)
The indices of SGPR register pairs need to be 2-aligned and SGPR
quadruplets need to be 4-aligned. With this patch, we report an error
when inline asm register constraints specify a misaligned register
index, instead of silently dropping the specified index.
Fixes #123208
---------
Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions