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authorCraig Topper <craig.topper@sifive.com>2025-06-25 23:09:24 -0700
committerGitHub <noreply@github.com>2025-06-25 23:09:24 -0700
commitc8243251cb25f3c171df16ff24ecbb39fbf68d4c (patch)
treeb26e2f60c21681323821cff5e172d6735a5c650c /llvm/lib/Bitcode/Reader/BitcodeReader.cpp
parenta6e524276e2c0596162a9635e0aa87a5ba145409 (diff)
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[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
This wasn't scalable and made the RISCVCC enum effectively just a different way of spelling the branch opcodes. This patch reduces RISCVCC back down to 6 enum values. The primary user is select pseudoinstructions which now share the same encoding across all vendor extensions. The select opcode and condition code are used to determine the branch opcode when expanding the pseudo. The Cond SmallVector returned by analyzeBranch now returns the opcode instead of the RISCVCC. reverseBranchCondition now works directly on opcodes. getOppositeBranchCondition is also retained. Stacked on #145622
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
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