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| author | Luke Lau <luke@igalia.com> | 2025-07-30 11:29:34 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-30 11:29:34 +0800 |
| commit | 9b23e2bf8d69909d959434da5ef392aefcd0b694 (patch) | |
| tree | 36974dc8bbfbf54e93eb35bea379addb884a72e5 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 8f09b03aebb71c154f3bbe725c29e3f47d37c26e (diff) | |
| download | llvm-9b23e2bf8d69909d959434da5ef392aefcd0b694.zip llvm-9b23e2bf8d69909d959434da5ef392aefcd0b694.tar.gz llvm-9b23e2bf8d69909d959434da5ef392aefcd0b694.tar.bz2 | |
[RISCV] Add copies to physical registers in VL optimizer tests. NFC (#151170)
In an upcoming patch to support recurrences in the RISCVVLOptimizer, we
need to perform an optimistic dataflow analysis where we assume
instructions have a DemandedVL of zero until a user is encountered.
Because of this if there's no "root" instruction, nothing will be
demanded and all the VLs will be set to zero.
This prepares for this by adding a copy to a physical register in the
MIR tests so that the behaviour is preserved, and matches whats
generated lowering from regular LLVM IR.
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions