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| author | Ties Stuij <ties@stuij.se> | 2023-01-05 11:19:56 +0000 |
|---|---|---|
| committer | Ties Stuij <ties@stuij.se> | 2023-01-05 11:50:31 +0000 |
| commit | 8d5b759a6c7abd47bdb9ae107584a991b182931e (patch) | |
| tree | ef37a9d54d1342d3906f2ccf79f6a0d13d867bcc /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 055fb7795aa219a3d274d280ec9129784f169f56 (diff) | |
| download | llvm-8d5b759a6c7abd47bdb9ae107584a991b182931e.zip llvm-8d5b759a6c7abd47bdb9ae107584a991b182931e.tar.gz llvm-8d5b759a6c7abd47bdb9ae107584a991b182931e.tar.bz2 | |
[AArch64][GlobalISel] implement GPR (U/S)(MIN/MAX) instr support
Lower umin, umax, smin, smax intrinsics to corresponding UMIN, UMAX, SMIN, SMAX
instructions when feat CSSC is available.
Reviewed By: aemerson
Differential Revision: https://reviews.llvm.org/D139420
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions