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authorLuke Lau <luke@igalia.com>2025-06-12 11:09:09 +0100
committerGitHub <noreply@github.com>2025-06-12 11:09:09 +0100
commit7ef77eb9984d1fb537a409cf4be89560fbb681fe (patch)
tree40f124347a3b2e11fddf20da07bbd4c543c17012 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp
parent5987f1ee5cc59a05961156c04010ab0f3c857628 (diff)
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[LV] Support scalable interleave groups for factors 3,5,6 and 7 (#141865)
Currently the loop vectorizer can only vectorize interleave groups for power-of-2 factors at scalable VFs by recursively interleaving [de]interleave2 intrinsics. However after https://github.com/llvm/llvm-project/pull/124825 and #139893, we now have [de]interleave intrinsics for all factors up to 8, which is enough to support all types of segmented loads and stores on RISC-V. Now that the interleaved access pass has been taught to lower these in #139373 and #141512, this patch teaches the loop vectorizer to emit these intrinsics for factors up to 8, which enables scalable vectorization for non-power-of-2 factors. As far as I'm aware, no in-tree target will vectorize a scalable interelave group above factor 8 because the maximum interleave factor is capped at 4 on AArch64 and 8 on RISC-V, and the `-max-interleave-group-factor` CLI option defaults to 8, so the recursive [de]interleaving code has been removed for now. Factors of 3 with scalable VFs are also turned off in AArch64 since there's no lowering for [de]interleave3 just yet either.
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