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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-02-10 11:58:05 +0000 |
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| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-02-10 12:14:26 +0000 |
| commit | 39eade73a5671724c8e4bf03f03359d84d8562b4 (patch) | |
| tree | 00a58ff99f4cc90724e842052a008e12f983ce65 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 2a3ef377ec00e7c7d3f4c47614ab6baee727cd82 (diff) | |
| download | llvm-39eade73a5671724c8e4bf03f03359d84d8562b4.zip llvm-39eade73a5671724c8e4bf03f03359d84d8562b4.tar.gz llvm-39eade73a5671724c8e4bf03f03359d84d8562b4.tar.bz2 | |
Revert rGe82e17d4d4cac8b2df00094e80d5e1cb22795664 - [X86] Add lowerShuffleAsBitRotate (PR44379)
As noted on PR44379, we didn't attempt to lower vector shuffles using bit rotations on XOP/AVX512F targets.
This patch lowers to uniform ISD:ROTL nodes - ROTR isn't supported by XOP and they are interchangeable for constant values anyway.
There might be cases where targets without ISD:ROTL support would benefit from this (expanding to SRL+SHL+OR), which I'll investigate in a future patch.
Also, non-AVX512BW targets fail to concatenate 256-bit rotations back to 512-bits (split during shuffle lowering as they don't have v32i16/v64i8 types).
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Internal shuffle tests indicate theres a bug somewhere that I haven't been able to track down yet.
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions