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| author | quic_hchandel <165007698+hchandel@users.noreply.github.com> | 2025-01-13 16:36:05 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-01-13 16:36:05 +0530 |
| commit | 171d3edd0507422f64cc11b33dac7b7f2b703f76 (patch) | |
| tree | f63c0314dccc49a00f3275a4c83d37db0d498892 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | d7e79663e77e05ed4e7580be1dca00d7ef3b12c5 (diff) | |
| download | llvm-171d3edd0507422f64cc11b33dac7b7f2b703f76.zip llvm-171d3edd0507422f64cc11b33dac7b7f2b703f76.tar.gz llvm-171d3edd0507422f64cc11b33dac7b7f2b703f76.tar.bz2 | |
[RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (#122256)
This extension adds eleven instructions to accelerate interrupt
servicing.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
---------
Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions