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| author | Craig Topper <craig.topper@sifive.com> | 2021-01-27 09:48:27 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-01-27 10:20:12 -0800 |
| commit | 04570e98c85f7cd35577f8193ac04ecd3bc38fea (patch) | |
| tree | d24994f5dbb281d2cf519064a42012cf7c9959f7 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | f30c523660106dd19072ae7baed72b18adfb0aa7 (diff) | |
| download | llvm-04570e98c85f7cd35577f8193ac04ecd3bc38fea.zip llvm-04570e98c85f7cd35577f8193ac04ecd3bc38fea.tar.gz llvm-04570e98c85f7cd35577f8193ac04ecd3bc38fea.tar.bz2 | |
[RISCV] Group the legal vector types into lists we can iterator over in the RISCVISelLowering constructor
Remove the RISCVVMVTs namespace because I don't think it provides
a lot of value. If we change the mappings we'd likely have to add
or remove things from the list anyway.
Add a wrapper around addRegisterClass that can determine the
register class from the fixed size of the type.
Reviewed By: frasercrmck, rogfer01
Differential Revision: https://reviews.llvm.org/D95491
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions