diff options
| author | Tony Tye <Tony.Tye@amd.com> | 2021-02-16 03:22:34 +0000 |
|---|---|---|
| committer | Tony Tye <Tony.Tye@amd.com> | 2021-02-17 01:32:29 +0000 |
| commit | c62b737ad655f189cf76f4324ba04317133d6648 (patch) | |
| tree | abed073242f69a7988b14563c4d915f875f070e5 /llvm/docs/CommandGuide | |
| parent | f456959a9331e628e8214930e6d4dceb34d75ea0 (diff) | |
| download | llvm-c62b737ad655f189cf76f4324ba04317133d6648.zip llvm-c62b737ad655f189cf76f4324ba04317133d6648.tar.gz llvm-c62b737ad655f189cf76f4324ba04317133d6648.tar.bz2 | |
[AMDGPU] Correct rmw atomics s_waitcnt generation
The AMD GPU SIMemoryLegalizer was using the ordering address space
rather than the instruction address space when determining the
s_waitcnt to generate to ensure that a read-modify-write atomic has
completed. This resulted in additional unnecessary counters being
waited on.
Differential Revision: https://reviews.llvm.org/D96743
Diffstat (limited to 'llvm/docs/CommandGuide')
0 files changed, 0 insertions, 0 deletions