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| author | Jay Foad <jay.foad@amd.com> | 2025-03-24 17:11:39 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-24 17:11:39 +0000 |
| commit | 02ed65912ea36ddbb280c959eebb5df129fa3dfa (patch) | |
| tree | fefe1b5fc0f645bb98b708d4ab5810c9a72e7355 /llvm/docs/CommandGuide | |
| parent | 34fa037c4fd7f38faada5beedc63ad234e904247 (diff) | |
| download | llvm-02ed65912ea36ddbb280c959eebb5df129fa3dfa.zip llvm-02ed65912ea36ddbb280c959eebb5df129fa3dfa.tar.gz llvm-02ed65912ea36ddbb280c959eebb5df129fa3dfa.tar.bz2 | |
[AMDGPU] 4-align TTMP triples (#132759)
Follow up to e4284a7c70cd "[AMDGPU] 4-align SGPR triples".
Previously TTMP triples like ttmp[3:5] were aligned on a 3-TTMP boundary
which has no basis in hardware.
Aligning them on a 4-TTMP boundary matches what we do for SGPRs, which
reduces the number of extra register classes synthesized by TableGen,
bringing the total number down from 653 to 615.
Diffstat (limited to 'llvm/docs/CommandGuide')
0 files changed, 0 insertions, 0 deletions