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| author | Qiu Chaofan <qiucofan@cn.ibm.com> | 2020-09-28 18:16:25 +0800 |
|---|---|---|
| committer | Qiu Chaofan <qiucofan@cn.ibm.com> | 2020-09-28 18:22:12 +0800 |
| commit | 40e86ca749a7c38875858d1005f34d1e2f53743b (patch) | |
| tree | ad1cdcfb3ed1bc9c550134fe37d87ae450bd7439 /lldb/unittests/ScriptInterpreter/Python | |
| parent | bab1a17ad7761ae61e5841c2fb905de59cb8c2da (diff) | |
| download | llvm-40e86ca749a7c38875858d1005f34d1e2f53743b.zip llvm-40e86ca749a7c38875858d1005f34d1e2f53743b.tar.gz llvm-40e86ca749a7c38875858d1005f34d1e2f53743b.tar.bz2 | |
[PowerPC] Clean-up mayRaiseFPException bits
According to POWER ISA, floating point instructions altering exception
bits in FPSCR should be 'may raise FP exception'. (excluding those
read or write the whole FPSCR directly, like mffs/mtfsf) We need to
model FPSCR well in future patches to handle the special case properly.
Instructions added mayRaiseFPException:
- fre(s)/frsqrte(s)
- fmadd(s)/fmsub(s)/fnmadd(s)/fnmsub(s)
- xscmpoqp/xscmpuqp/xscmpeqdp/xscmpgedp/xscmpgtdp
- xscvdphp/xscvhpdp/xvcvhpsp/xvcvsphp/xsrqpxp
- xsmaxcdp/xsincdp/xsmaxjdp/xsminjdp
Instructions removed mayRaiseFPException:
- xstdivdp/xvtdiv(d|s)p/xstsqrtdp/xvtsqrt(d|s)p
- xsabsdp/xsnabsdp/xvabs(d|s)p/xvnabs(d|s)p
- xsnegdp/xscpsgndp/xvneg(d|s)p/xvcpsgn(d|s)p
- xvcvsxwdp/xvcvuxwdp
- xscvdpspn/xscvspdpn
Reviewed By: steven.zhang
Differential Revision: https://reviews.llvm.org/D87738
Diffstat (limited to 'lldb/unittests/ScriptInterpreter/Python')
0 files changed, 0 insertions, 0 deletions