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| author | Changpeng Fang <changpeng.fang@amd.com> | 2025-07-30 12:24:51 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-30 12:24:51 -0700 |
| commit | 180281b8eccfa8e1ec4ebc58df7685497f9ccb26 (patch) | |
| tree | 3fa3efcb49518f1c7875fb8c1e2ed87adc72f6c6 /lldb/unittests/ScriptInterpreter/Python | |
| parent | 953be42e407593b5c5dd17283e2b0f8f7f7f4d6d (diff) | |
| download | llvm-180281b8eccfa8e1ec4ebc58df7685497f9ccb26.zip llvm-180281b8eccfa8e1ec4ebc58df7685497f9ccb26.tar.gz llvm-180281b8eccfa8e1ec4ebc58df7685497f9ccb26.tar.bz2 | |
[AMDGPU] Fix op_sel settings for v_cvt_scale32_* and v_cvt_sr_* (#151286)
For OPF_OPSEL_SRCBYTE: Vector instruction uses OPSEL[1:0] to specify a
byte
select for the first source operand. So op_sel [0, 0], [1, 0], [0, 1]
and [1, 1] should map
to byte 0, 1, 2 and 3, respectively.
For OPF_OPSEL_DSTBYTE: OPSEL is used as a destination byte select.
OPSEL[2:3]
specify which byte of the destination to write to. Note that the order
of the bits is different
from that of OPF_OPSEL_SRCBYT. So the mapping should be: op_sel [0, 0],
[0, 1], [1, 0]
and [1, 1] map to byte 0, 1, 2 and 3, respectively.
Fixes: SWDEV-544901
Diffstat (limited to 'lldb/unittests/ScriptInterpreter/Python')
0 files changed, 0 insertions, 0 deletions