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| author | Andrew Savonichev <andrew.savonichev@gmail.com> | 2021-11-10 19:02:27 +0300 |
|---|---|---|
| committer | Andrew Savonichev <andrew.savonichev@gmail.com> | 2021-11-10 19:05:03 +0300 |
| commit | 00aa0aeb067bbfda274aafdcabe9f058959db66b (patch) | |
| tree | edc26421adbca29275fb52f7e8298dd627ed4b7f /lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp | |
| parent | 4e2c978f440fb791b84258234a0d3b00c36ce6a4 (diff) | |
| download | llvm-00aa0aeb067bbfda274aafdcabe9f058959db66b.zip llvm-00aa0aeb067bbfda274aafdcabe9f058959db66b.tar.gz llvm-00aa0aeb067bbfda274aafdcabe9f058959db66b.tar.bz2 | |
[NVPTX] Add imm variants for surface and texture instructions
Texture/sampler/surface operands can be either a register or an
immediate (an index of .texref, .samplerref or .surfref).
TableGen declarations for these instructions used to only have
Int64Regs operands, so this caused issues when machine verifier
is turned on:
*** Bad machine code: Expected a register operand. ***
- function: bar
- basic block: %bb.0 (0x55b144d99ab8)
- instruction: %4:int32regs = SULD_1D_I32_TRAP 0, killed %2:int32regs
- operand 1: 0
The solution is to duplicate these instructions for all possible
operand types (i16imm and Int64Regs). Since this would
essentially double the amount code in TableGen, the patch also
does some refactoring for the original instructions to keep
things manageable.
Differential Revision: https://reviews.llvm.org/D112232
Diffstat (limited to 'lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp')
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