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| author | Luke Lau <luke@igalia.com> | 2023-03-09 16:18:28 +0000 |
|---|---|---|
| committer | Luke Lau <luke@igalia.com> | 2023-03-15 21:56:30 +0000 |
| commit | acc03ad10af4f379a644e3956cb9aca54e40696c (patch) | |
| tree | b7555787373dd875195d556e145c420aad60f565 /lldb/unittests/ScriptInterpreter/Python/PythonDataObjectsTests.cpp | |
| parent | 765d8a192180f8f33618087b15c022fe758044af (diff) | |
| download | llvm-acc03ad10af4f379a644e3956cb9aca54e40696c.zip llvm-acc03ad10af4f379a644e3956cb9aca54e40696c.tar.gz llvm-acc03ad10af4f379a644e3956cb9aca54e40696c.tar.bz2 | |
[RISCV] Enable interleaved access vectorization
The loop vectorizer supports generating interleaved loads and stores via
shuffle patterns for fixed length vectors.
This enables it for RISC-V, since interleaved shuffle patterns can be
lowered to vlseg/vsseg in https://reviews.llvm.org/D145022
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D145155
Diffstat (limited to 'lldb/unittests/ScriptInterpreter/Python/PythonDataObjectsTests.cpp')
0 files changed, 0 insertions, 0 deletions