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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2021-05-25 18:00:53 +0100 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2021-05-26 10:30:59 +0100 |
| commit | 66978466baefbaac3234df07851ec6d94f99914c (patch) | |
| tree | ddfc06f6989c5f912b8df8912e40014645b2bffa /lldb/source/Target/ModuleCache.cpp | |
| parent | 794fb5482efc4af5434e23efb5b0a99b4a386eed (diff) | |
| download | llvm-66978466baefbaac3234df07851ec6d94f99914c.zip llvm-66978466baefbaac3234df07851ec6d94f99914c.tar.gz llvm-66978466baefbaac3234df07851ec6d94f99914c.tar.bz2 | |
[X86][Atom] Fix vector variable shift resource/throughputs
Match whats documented in the Intel AOM - the non-immediate variants of the PSLL*/PSRA*/PSRL* shift instructions requires BOTH ports - this was being incorrectly modelled as EITHER port.
Now that we can use in-order models in llvm-mca, the atom model is a good "worst case scenario" analysis for x86.
Diffstat (limited to 'lldb/source/Target/ModuleCache.cpp')
0 files changed, 0 insertions, 0 deletions