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| author | zhongyunde <zhongyunde@huawei.com> | 2022-03-15 01:19:39 +0800 |
|---|---|---|
| committer | zhongyunde <zhongyunde@huawei.com> | 2022-03-15 01:25:03 +0800 |
| commit | 3568333815b30dc565ce041c64e871bc1d4e8e21 (patch) | |
| tree | 84fc9e64ca32c5ddf5932ce5b9fe23ba9ce5dfe6 /lldb/source/Commands/CommandObjectThread.cpp | |
| parent | cf63e9d4caccbd540df083c63a5217ac50b5e1f9 (diff) | |
| download | llvm-3568333815b30dc565ce041c64e871bc1d4e8e21.zip llvm-3568333815b30dc565ce041c64e871bc1d4e8e21.tar.gz llvm-3568333815b30dc565ce041c64e871bc1d4e8e21.tar.bz2 | |
[AArch64] Perform last active true vector combine
Test bit of lane EC-1 can use P register directly, eg:
Materialize : Idx = (add (mul vscale, NumEls), -1)
i1 = extract_vector_elt t37, Constant:i64<Idx>
... into: "ptrue p, all" + PTEST
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D121180
Diffstat (limited to 'lldb/source/Commands/CommandObjectThread.cpp')
0 files changed, 0 insertions, 0 deletions