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| author | Oliver Stannard <oliver.stannard@arm.com> | 2018-09-26 15:42:47 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2018-09-26 15:42:47 +0000 |
| commit | 2905937435ccda087a9c915aca8bfa8878a645a6 (patch) | |
| tree | 79d65e43bb2014497bb210195dfadc3ae7bd2fec /lldb/source/Commands/CommandObjectThread.cpp | |
| parent | 3b4d331d8cbd72078ae9fff1b81ca96c0d55ecb8 (diff) | |
| download | llvm-2905937435ccda087a9c915aca8bfa8878a645a6.zip llvm-2905937435ccda087a9c915aca8bfa8878a645a6.tar.gz llvm-2905937435ccda087a9c915aca8bfa8878a645a6.tar.bz2 | |
[AArch64] Extend single-operand FP insns to match Arm ARM (NFCI)
The Armv8.3-A reference manual defines floating-point data-processing
instructions with one source operand to have an opcode of 6 bits
[20:15]. The current class in tablegen, BaseSingleOperandFPData, only
allows [18:15]. This was ok because [20:19] could only be '00', with
other encodings unallocated. Armv8.5-A brings in the FRINT group of
instructions which use other values for these bits.
This patch refactors the existing class a bit to allow using the full 6
bits of the opcode, as defined in the Arm ARM.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52474
llvm-svn: 343120
Diffstat (limited to 'lldb/source/Commands/CommandObjectThread.cpp')
0 files changed, 0 insertions, 0 deletions