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authorMichael Maitland <michaeltmaitland@gmail.com>2023-05-05 10:12:40 -0700
committerMichael Maitland <michaeltmaitland@gmail.com>2023-05-05 10:16:35 -0700
commitf9fa8a59970451ffd9ffc6b4c0554c7e7bd25ab0 (patch)
tree2d54c835eaeb2f931dc1d43d03f63f78496392f3 /lldb/source/Commands/CommandObjectSource.cpp
parent0b3d737877040a4eae03e47223f9a9ddfd7bd182 (diff)
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[RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td
Based on the following description from Andrew W. Instructions not mentioned here behave the same as integer ALU ops rev8 only executes in the late-A and late-B ALUs shNadd[.uw] only execute on the early-B and late-B ALUs clz[w], ctz[w], and orc.b and all rotates only execute in the late-B ALU pcnt[w] looks exactly like integer multiply This patch does not account for early/late ALU in the model. It is coded based on the pipes only. Co-Authored-By: topperc <craig.topper@sifive.com> Differential Revision: https://reviews.llvm.org/D149497
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