[RISCV][ISel] Allow emitting `addiw` with u32simm12 rhs (#111116)

In InstCombine, we shrink the constant by setting unused bits to zero
(e.g. `((X + -2) & 4294967295) -> ((X + 4294967294) & 4294967295)`).
However, this canonicalization blocks emitting `addiw` and creates
redundant li for simm32 rhs:
```
; bin/llc -mtriple=riscv64 -mattr=+zba test.ll -o -
define i64 @add_u32simm32_zextw(i64 %x) nounwind {
entry:
  %add = add i64 %x, 4294967294
  %and = and i64 %add, 4294967295
  ret i64 %and
}
```
```
add_u32simm32_zextw:                    # @add_u32simm32_zextw
# %bb.0:                                # %entry
        li      a1, -2
        add     a0, a0, a1
        zext.w  a0, a0
        ret
```

This patch addresses the issue by matching u32simm12 rhs.

0 files changed, 0 insertions, 0 deletions