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| author | Craig Topper <craig.topper@sifive.com> | 2022-06-23 08:41:12 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-06-23 08:49:18 -0700 |
| commit | 8b10ffabae48ae6eae5ece711c13b93f9c232515 (patch) | |
| tree | 036185b933e00ee44d3d6b1de2c7a497bb0c6d6d /lldb/source/Commands/CommandObjectLog.cpp | |
| parent | 0ec87addb7d17b45f68e003e22e96d479a70b070 (diff) | |
| download | llvm-8b10ffabae48ae6eae5ece711c13b93f9c232515.zip llvm-8b10ffabae48ae6eae5ece711c13b93f9c232515.tar.gz llvm-8b10ffabae48ae6eae5ece711c13b93f9c232515.tar.bz2 | |
[RISCV] Disable <vscale x 1 x *> types with Zve32x or Zve32f.
According to the vector spec, mf8 is not supported for i8 if ELEN
is 32. Similarily mf4 is not suported for i16/f16 or mf2 for i32/f32.
Since RVVBitsPerBlock is 64 and LMUL is calculated as
((MinNumElements * ElementSize) / RVVBitsPerBlock) this means we
need to disable any type with MinNumElements==1.
For generic IR, these types will now be widened in type legalization.
For RVV intrinsics, we'll probably hit a fatal error somewhere. I plan
to work on disabling the intrinsics in the riscv_vector.h header.
Reviewed By: arcbbb
Differential Revision: https://reviews.llvm.org/D128286
Diffstat (limited to 'lldb/source/Commands/CommandObjectLog.cpp')
0 files changed, 0 insertions, 0 deletions