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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-10-30 12:56:24 -0700 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2019-10-30 14:56:33 -0700 |
| commit | d9e0a2942ac71327166a3a597e8383192fd19b17 (patch) | |
| tree | 87a2c8acdcce7a7e7a8857abe0a1b98b90ea189d /lldb/source/Commands/CommandObjectBreakpointCommand.cpp | |
| parent | 204a529cb0d6b67eb66d81a07e11a2df00e22764 (diff) | |
| download | llvm-d9e0a2942ac71327166a3a597e8383192fd19b17.zip llvm-d9e0a2942ac71327166a3a597e8383192fd19b17.tar.gz llvm-d9e0a2942ac71327166a3a597e8383192fd19b17.tar.bz2 | |
AMDGPU: Disallow spill folding with m0 copies
readlane and writelane instructions are not allowed to use m0 as the
data operand, so spilling them is tricky and would require an
intermediate SGPR to spill it. Constrain the virtual register class in
this caes to disallow the inline spiller from folding the m0 operand
directly into the spill instruction.
I copied this hack from AArch64 which has the same problem for $sp.
Diffstat (limited to 'lldb/source/Commands/CommandObjectBreakpointCommand.cpp')
0 files changed, 0 insertions, 0 deletions