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| author | Craig Topper <craig.topper@intel.com> | 2019-10-30 14:56:19 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-10-30 15:07:49 -0700 |
| commit | 8f48ba993ba32925f37a374f624663da37d96254 (patch) | |
| tree | af43438b93c0c65c36ed4c8d6389c9da4d88717b /lldb/source/Commands/CommandObjectBreakpointCommand.cpp | |
| parent | 812bdb3c13210759341e8a1b08b864a539ce9dc7 (diff) | |
| download | llvm-8f48ba993ba32925f37a374f624663da37d96254.zip llvm-8f48ba993ba32925f37a374f624663da37d96254.tar.gz llvm-8f48ba993ba32925f37a374f624663da37d96254.tar.bz2 | |
[X86] Model MXCSR for all SSE instructions
This patch adds MXCSR as a reserved physical register and models its use
by X86 SSE instructions. It also adds flag "mayRaiseFPException" for the
instructions that possibly can raise FP exception according to the
architecture definition.
Following what SystemZ and other targets does, only the current rounding
modes and the IEEE exception masks are modeled. *Changes* of the MXCSR
due to exceptions are not modeled.
Patch by Pengfei Wang
Differential Revision: https://reviews.llvm.org/D68121
Diffstat (limited to 'lldb/source/Commands/CommandObjectBreakpointCommand.cpp')
0 files changed, 0 insertions, 0 deletions