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| author | Brox Chen <guochen2@amd.com> | 2025-07-09 16:17:14 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-09 16:17:14 -0400 |
| commit | 0d2b47ae4a01fd97fe479806a45a535ad347eb63 (patch) | |
| tree | f26392bfb44135ce6455454df2b1db5af8b94e8c /lldb/source/Commands/CommandObjectBreakpoint.cpp | |
| parent | 702784ca7661fe1d0bc9dc81c0ceabfa82e4a37e (diff) | |
| download | llvm-0d2b47ae4a01fd97fe479806a45a535ad347eb63.zip llvm-0d2b47ae4a01fd97fe479806a45a535ad347eb63.tar.gz llvm-0d2b47ae4a01fd97fe479806a45a535ad347eb63.tar.bz2 | |
[AMDGPU][True16][CodeGen] stop emitting spgr_lo16 from isel (#144819)
When true16 is enabled, isel start to emit sgpr_lo16 register when a
trunc/sext i16/i32 is generated, or a salu32 is used by vgpr16 or vice
versa. And this causes a problem as sgpr_lo16 is not fully supported in
the pipeline.
True16 mode works fine in -O3 mode since folding pass remove sgpr_lo16
from the pipeline. However it hit a problem in -O0 mode as folding pass
is skipped.
This patch did:
1. stop emitting sgpr_lo16 from isel
2. update codegen pattern to split uniformed/divergent pattern for
i16/i32 conversion
3. update fix-sgpr-copy pass to address legalization requirement in
true16 mode, update fix-sgpr-copies-f16-true16.mir
test to include all possible combinations
This patch is tested with cts and downstream repo with -O0 testing
Diffstat (limited to 'lldb/source/Commands/CommandObjectBreakpoint.cpp')
0 files changed, 0 insertions, 0 deletions